1. Field of the Invention
The present invention relates to the design of programmable logic devices and, in particular, relates to the programming of programmable logic devices.
2. Discussion of the Related Art
Unlike a conventional programmable logic device, an in-system programmable logic device (ISPLD) may be reprogrammed in its application without removal from the circuit board. Some ISPLD devices, such as those available from Lattice Semiconductor Corporation, Hillsboro, Oreg., can be reprogrammed using an operating power supply rather than a high programming voltage. The method of reprogramming an ISPLD in place is known in the art as in-system programming (ISP). FIG. 1 shows an idealized pin-out of a typical ISPLD 5. As shown in FIG. 1, ISPLD 5 comprises a number of input-only pins (I.sub.1, I.sub.2, . . . , I.sub.n), a number of programmable input/output pins (I/O.sub.1, I/O.sub.2, . . . , I/O.sub.m), power (VCC) and ground (GND) pins, and a set of four ISP pins (SDI, SDO, SCLK, and MODE).
To reprogram ISPLD 5 using ISP, a host system including a microprocessor or microcontroller and a signal source (which is well known and thus not shown for simplicity) converts the desired programming parameters into a JEDEC file using a design tool such as Synario/pDS available from Lattice Semiconductor Corporation. This JEDEC file is then converted to a binary file such as, for instance, an ispSTREAM file using software such as JED2ISP Conversion Utility available from Lattice Semiconductor Corporation. In response to this ispSTREAM file, an isp signal source provides programming data and programming control signals to ISPLD 5 at pins SDI, SCLK, and MODE, respectively, and receives signals from ISPLD 5 indicative of, for instance, programming verification or self-test at pin SDO. Typically, where for example the host system is a PC-based machine, an 8-bit parallel port serves as the interface between the host system and ISPLD 5. In such cases, where only four of the 8-bits of the parallel port are utilized, ISPLD 5 is said to employ a four-wire interface.
In the ISP mode, a state machine within ISPLD 5 having numerous states takes over control of the programming activities. Programming data generated by the host system is input serially into the program memory of ISPLD 5 over the serial input pin SDI via the parallel interface. The rate of serial input is 1-bit per clock period. A clock signal is provided on pin SCLK when the ISP mode is entered. Each ISPLD 5 can, in a mode operation referred to as Flowthrough mode, provide on its output pin SDO data received from its serial input pin SDI. In this manner, a number of ISPLDs 5 may be "daisy-chained" together by tying the serial input pin SDI of one ISPLD 5 to the serial output pin SDO of another ISPLD 5. Any ISPLD 5 in the daisy chain can be re-programmed by providing the new program to the serial input pin SDI of the first ISPLD 5, where the data is then provided to the ISPLD 5 desired to be programmed by shifting the data through intervening ISPLDs 5 (which are placed in Flowthrough mode) in the daisy chain.
In-system programming techniques for ISPLDs employing a four-wire ISP parallel interface such as ISPLD 5 are discussed further in U.S. Pat. Nos. 4,855,954 (entitled "In-System Programmable Logic Device with Four Dedicated Terminals", to Turner et al, issued Aug. 8, 1989), 4,761,768 (entitled "Programmable Logic Device", to Turner et al, issued Aug. 2, 1988), and 4,896,296 (entitled "Programmable Logic Device Configurable I/O Cell", to Turner et al, issued Jan. 23, 1990).
More recent ISPLDs reduce total pin overhead by employing only one dedicated programming pin, e.g., the in-system programming or ispEN pin. When an enabling signal associated with the ispEN pin is asserted, this ISPLD enters a programming mode. The additional in-system programming pins (SDI, SDO, SCLK, and MODE) referred to above are made available by multiplexing pins which are normally, i.e., when not in programming mode, input/output pins. In-system programming may thus be implemented at the cost of only a single dedicated pin. For a more detailed explanation of programming techniques using only one dedicated programming pin ispEN, see U.S. Pat. No. 5,237,218 (entitled "Structure and Method for Multiplexing Pins for In-System Programming", to Josephson et al, issued Aug. 17, 1993), hereby incorporated by reference. Note that when ISPLDs having a dedicated programming pin ispEN are in a programming state, the use of five pins (ispEN, SDI, SDO, SCLK, and MODE) are required. Accordingly, such ISPLDs require a five-wire interface.
It is thus desirable to implement a system capable of providing program data to and receive response data from a PLD using a two-wire transmission means. In this manner, transmission techniques such as standard telephone lines and wireless communications may be employed to remotely program the ISPLD.